1. Field of the Invention
The present invention relates to implementing a multiplexer using a small set of resources on a programmable chip. In one example, the present invention relates to methods and apparatus for efficiently implementing a 3:1 multiplexer using minimal resources.
2. Description of Related Art
Conventional processors including general purpose processors, digital signal processors, video accelerators, and other hardware devices typically use multiplexer circuitry. Multiplexer circuitry allows one of multiple input lines to be selected for output based on control information. One particular multiplexer that is often used is a 3:1 multiplexer. A 3:1 multiplexer allows selection of one of three inputs for output based on control information usually provided by two control lines.
Multiplexers are implemented in a variety of manners. For devices such as application specific integrated circuits (ASICs), multiplexers are relatively inexpensive to implement. However, on devices such us field programmable gate arrays (FPGAs) or other programmable chips, multiplexers can be more resource intensive and can also introduce undesired delay into a processing data path. Conventional mechanisms for implementing multiplexers such as 3:1 multiplexers are relatively limited.
Consequently, the techniques of the present invention provide mechanisms for improving the efficiency of multiplexer implementation on programmable chips.